1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficient instruction support of an increasing number of available features for an instruction set.
2. Description of the Relevant Art
Typically, instruction sets tend to have a limited opcode space. However, processors are continually introducing a wide variety of multi-function instructions, which are consuming available opcodes, in order to ensure performance leadership in key application spaces. Future processors may easily reduce the complexity and performance of the hardware associated with newer instructions, or deprecate older, less utilized instructions, by using a trap-and-emulate mechanism. However, the opcodes themselves cannot be reused for other purposes for a very long period of time, such as multiple processor generations. Also, the new features of interest supported by the multi-function instructions can be very application-space dependent. For example, new features and the corresponding multi-function instructions in the telecommunication space may be completely unused in the enterprise space. Therefore, the consumption of limited available opcodes may not be efficient.
In addition, although some multi-function instructions may remain useful for a significant period of time, other multi-function instructions may be associated with features that soon become outdated. One example is instructions that target cryptographic acceleration. In this space, ciphers age. Once important cipher algorithms rapidly lose importance as newer, stronger, and more efficient ciphers are invented and standardized. As a result, a processor, which supports instructions targeted at cryptographic ciphers, has an opcode space that will, over time, become littered with old out-of-date opcodes supporting out-of-date ciphers. Therefore, newer generations of instruction sets may have less opcode space for implementing newer features.
While increasing the instruction size, such as increasing from a 32-bit instruction size to a 64-bit instruction size, may resolve these problems, this solution is a very intrusive modification for customers to make. In addition, given the size of all instructions potentially increase, an application's instruction footprint becomes much larger. This overall size increase has a detrimental performance impact, especially in high multi-threaded processors with limited cache size.
Accordingly, increasing an instruction size is not a flexible scheme allows processors to introduce instruction-based support for features that are of only transient interest and then rapidly reuse the opcode space for newer instructions in a seamless manner.
In view of the above, efficient methods and mechanisms for efficient instruction support of an increasing number of available features for an instruction set are desired.